1. Field of the Invention
The present invention relates to a wireless communication system. More particularly, the present invention relates to a Phase Locked Loop (PLL) digitally implemented in a wireless communication system.
2. Description of the Related Art
A PLL is widely used to generate a carrier of an application in a 4-th Generation (4G) system such as a Long Term Evolution (LTE), a cellular phone such as Bluetooth, a Global Positioning System (GPS), a Wideband Code Division Multiple Access (WCDMA), and a wireless Local Area Network (LAN) such as 802.11a/b/g.
In the conventional analog PLL, since a divider should operate in high speed and includes a current source and cannot use a Width-to-Length (W/L) ratio of Metal Oxide Semiconductor (MOS) minimally depending on a noise and accuracy issue, an area cannot reduce remarkably when a process is scaled down. Since a loop filter includes a passive resistor and a capacitor, it requires a wide area. Also, since an analog signal level is important, a plurality of buffers such as a Voltage-Controlled Oscillator (VCO) buffer, a Local Oscillator (LO) buffer, an Output buffer, etc. are used, so that current consumption becomes very large. Furthermore, since an analog PLL is sensitive to a process characteristic, almost all blocks should be redesigned when a process changes or is scaled down, so that much time is taken in manufacturing and manufacturing costs increase. Also, as a fractional PLL is used due to a problem of a channel interval of a Radio Frequency (RF) band and a PLL bandwidth, a sigma-delta modulator is used to implement a divider of a fractional ratio. Accordingly, a divider circuit is complicated and power consumption and an area increase.